PRALU language - the tool for verifying digital devices
The task of creating a testbench for functional verification is considered. This verification process establishes the reconvergence (equivalence) of the device specification and the register-transfer level (RTL) model - a logical network which was built in the synthesis process. In the UVM methodolo...
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| Natura: | Articolo |
| Lingua: | Russian |
| Pubblicazione: |
National Academy of Sciences of Belarus, the United Institute of Informatics Problems
2018-12-01
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| Serie: | Informatika |
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| Accesso online: | https://inf.grid.by/jour/article/view/427 |