Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical pe...
| Main Authors: | , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9641815/ |
| _version_ | 1819098020828938240 |
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| author | Jin Park Min Su Cho Sang Ho Lee Hee Dae An So Ra Min Geon Uk Kim Young Jun Yoon Jae Hwa Seo Sin-Hyung Lee Jaewon Jang Jin-Hyuk Bae In Man Kang |
| author_facet | Jin Park Min Su Cho Sang Ho Lee Hee Dae An So Ra Min Geon Uk Kim Young Jun Yoon Jae Hwa Seo Sin-Hyung Lee Jaewon Jang Jin-Hyuk Bae In Man Kang |
| author_sort | Jin Park |
| collection | DOAJ |
| description | In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions. IG has an asymmetric structure with an underlap (<inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {underlap}}$ </tex-math></inline-formula>) region to reduce the Shockley–Read–Hall (SRH) recombination rate. In the proposed 1T-DRAM, the write “1” operation is performed by band-to-band tunneling between the OG and the IG. The proposed 1T-DRAM cell exhibited a sensing margin of <inline-formula> <tex-math notation="LaTeX">$422 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and a retention time of 120 ms at <inline-formula> <tex-math notation="LaTeX">$T$ </tex-math></inline-formula> = 358 K. |
| first_indexed | 2024-12-22T00:24:21Z |
| format | Article |
| id | doaj.art-5ccd72a798794e9ea26e6f74c9a37d5d |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-22T00:24:21Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-5ccd72a798794e9ea26e6f74c9a37d5d2022-12-21T18:45:05ZengIEEEIEEE Access2169-35362021-01-01916367516368510.1109/ACCESS.2021.31335729641815Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube StructureJin Park0https://orcid.org/0000-0003-1742-7572Min Su Cho1https://orcid.org/0000-0002-9372-6796Sang Ho Lee2https://orcid.org/0000-0002-4954-3861Hee Dae An3So Ra Min4Geon Uk Kim5Young Jun Yoon6Jae Hwa Seo7Sin-Hyung Lee8https://orcid.org/0000-0002-8723-439XJaewon Jang9https://orcid.org/0000-0003-1908-0015Jin-Hyuk Bae10https://orcid.org/0000-0003-3217-1309In Man Kang11https://orcid.org/0000-0002-7726-9740School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaKorea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongju, Republic of KoreaPower Semiconductor Research Center, Korea Electrotechnology Research Institute, Changwon, Republic of KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaIn this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions. IG has an asymmetric structure with an underlap (<inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {underlap}}$ </tex-math></inline-formula>) region to reduce the Shockley–Read–Hall (SRH) recombination rate. In the proposed 1T-DRAM, the write “1” operation is performed by band-to-band tunneling between the OG and the IG. The proposed 1T-DRAM cell exhibited a sensing margin of <inline-formula> <tex-math notation="LaTeX">$422 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and a retention time of 120 ms at <inline-formula> <tex-math notation="LaTeX">$T$ </tex-math></inline-formula> = 358 K.https://ieeexplore.ieee.org/document/9641815/Polycrystalline siliconone-transistor dynamic random-access memorygrain boundarynanotubemetal–oxide–semiconductor field-effect transistordual-gate |
| spellingShingle | Jin Park Min Su Cho Sang Ho Lee Hee Dae An So Ra Min Geon Uk Kim Young Jun Yoon Jae Hwa Seo Sin-Hyung Lee Jaewon Jang Jin-Hyuk Bae In Man Kang Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure IEEE Access Polycrystalline silicon one-transistor dynamic random-access memory grain boundary nanotube metal–oxide–semiconductor field-effect transistor dual-gate |
| title | Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure |
| title_full | Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure |
| title_fullStr | Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure |
| title_full_unstemmed | Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure |
| title_short | Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure |
| title_sort | design of capacitorless dram based on polycrystalline silicon nanotube structure |
| topic | Polycrystalline silicon one-transistor dynamic random-access memory grain boundary nanotube metal–oxide–semiconductor field-effect transistor dual-gate |
| url | https://ieeexplore.ieee.org/document/9641815/ |
| work_keys_str_mv | AT jinpark designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT minsucho designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT sangholee designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT heedaean designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT soramin designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT geonukkim designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT youngjunyoon designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT jaehwaseo designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT sinhyunglee designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT jaewonjang designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT jinhyukbae designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure AT inmankang designofcapacitorlessdrambasedonpolycrystallinesiliconnanotubestructure |