Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration wi...

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Bibliographic Details
Main Authors: Pooja Batra, Spyridon Skordas, Douglas LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, Wei Lin, Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, Brown Peethala, John Barth, Toshiaki Kirihata, Troy Graves-Abe, Norman Robson, Subramanian Iyer
Format: Article
Language:English
Published: MDPI AG 2014-05-01
Series:Journal of Low Power Electronics and Applications
Subjects:
EDRAM
3D
SOI
through-silicon-via (TSV)
wafer stacking
Online Access:http://www.mdpi.com/2079-9268/4/2/77

Internet

http://www.mdpi.com/2079-9268/4/2/77

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