An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor

An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor

In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In-memory Dot Product (IMDP) operations. The aver...

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Bibliographic Details
Main Authors: Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
Format: Article
Language:English
Published: Elsevier 2023-10-01
Series:Memories - Materials, Devices, Circuits and Systems
Subjects:
SRAM
von-Neumann architecture (VNA)
In-Memory Computing (IMC)
Energy-efficiency
Online Access:http://www.sciencedirect.com/science/article/pii/S2773064623000531

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http://www.sciencedirect.com/science/article/pii/S2773064623000531

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