An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor
In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In-memory Dot Product (IMDP) operations. The aver...
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| Format: | Article |
| Language: | English |
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Elsevier
2023-10-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064623000531 |
| _version_ | 1797656117892874240 |
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| author | Anil Kumar Rajput Manisha Pattanaik Gaurav Kaushal |
| author_facet | Anil Kumar Rajput Manisha Pattanaik Gaurav Kaushal |
| author_sort | Anil Kumar Rajput |
| collection | DOAJ |
| description | In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In-memory Dot Product (IMDP) operations. The average write margin and read margins of the proposed 10T SRAM are improved by 40% and 2.5%, respectively, compared to the 9T SRAM. The write energy and leakage power of the proposed 10T SRAM are reduced by 89% and 83.8%, respectively, with aproximatelly similar read energy compared to 9T SRAM. Additionally, a 4 Kb SRAM array based on 10T SRAM is implemented in 180-nm SCL technology to analyze the operation and performance of the proposed IMC macro architecture. The proposed IMC architecture achieves an energy efficiency of 5.3 TOPS/W for 1-bit logic, 4.1 TOPS/W for 1-bit addition, and 3.1 TOPS/W for IMDP operations at 1.8 V and 60 MHz. The area efficiency of 65.2% is achieved for a 136 × 32 array of proposed IMC macro architecture. Further, the proposed IMC macro is also tested for accelerating the IMDP operation of neural networks by importing linearity variation analysis in Tensorflow for image classification on MNIST and CIFAR datasets. According to Monte-Carlo simulations, the IMDP operation has a standard deviation of 0.07 percent in accumulation, equating to a classification accuracy of 97.02% on the MNIST dataset and 88.39% on the CIFAR dataset. |
| first_indexed | 2024-03-11T17:24:43Z |
| format | Article |
| id | doaj.art-5d63f18bc7f74cafb4aa97c6a9848c92 |
| institution | Directory Open Access Journal |
| issn | 2773-0646 |
| language | English |
| last_indexed | 2024-03-11T17:24:43Z |
| publishDate | 2023-10-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj.art-5d63f18bc7f74cafb4aa97c6a9848c922023-10-19T04:23:08ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462023-10-015100076An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processorAnil Kumar Rajput0Manisha Pattanaik1Gaurav Kaushal2Corresponding author.; VLSI Design Lab, ABV-IIITM, Gwalior, IndiaVLSI Design Lab, ABV-IIITM, Gwalior, IndiaVLSI Design Lab, ABV-IIITM, Gwalior, IndiaIn-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In-memory Dot Product (IMDP) operations. The average write margin and read margins of the proposed 10T SRAM are improved by 40% and 2.5%, respectively, compared to the 9T SRAM. The write energy and leakage power of the proposed 10T SRAM are reduced by 89% and 83.8%, respectively, with aproximatelly similar read energy compared to 9T SRAM. Additionally, a 4 Kb SRAM array based on 10T SRAM is implemented in 180-nm SCL technology to analyze the operation and performance of the proposed IMC macro architecture. The proposed IMC architecture achieves an energy efficiency of 5.3 TOPS/W for 1-bit logic, 4.1 TOPS/W for 1-bit addition, and 3.1 TOPS/W for IMDP operations at 1.8 V and 60 MHz. The area efficiency of 65.2% is achieved for a 136 × 32 array of proposed IMC macro architecture. Further, the proposed IMC macro is also tested for accelerating the IMDP operation of neural networks by importing linearity variation analysis in Tensorflow for image classification on MNIST and CIFAR datasets. According to Monte-Carlo simulations, the IMDP operation has a standard deviation of 0.07 percent in accumulation, equating to a classification accuracy of 97.02% on the MNIST dataset and 88.39% on the CIFAR dataset.http://www.sciencedirect.com/science/article/pii/S2773064623000531SRAMvon-Neumann architecture (VNA)In-Memory Computing (IMC)Energy-efficiency |
| spellingShingle | Anil Kumar Rajput Manisha Pattanaik Gaurav Kaushal An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor Memories - Materials, Devices, Circuits and Systems SRAM von-Neumann architecture (VNA) In-Memory Computing (IMC) Energy-efficiency |
| title | An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor |
| title_full | An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor |
| title_fullStr | An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor |
| title_full_unstemmed | An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor |
| title_short | An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor |
| title_sort | energy efficient 10t sram in memory computing macro for artificial intelligence edge processor |
| topic | SRAM von-Neumann architecture (VNA) In-Memory Computing (IMC) Energy-efficiency |
| url | http://www.sciencedirect.com/science/article/pii/S2773064623000531 |
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