Low-Latency and Minor-Error Architecture for Parallel Computing <i>X<sup>Y</sup></i>-like Functions with High-Precision Floating-Point Inputs

Low-Latency and Minor-Error Architecture for Parallel Computing <i>X<sup>Y</sup></i>-like Functions with High-Precision Floating-Point Inputs

This paper proposes a novel architecture for the computation of <i>X<sup>Y</sup></i>-like functions based on the QH CORDIC (Quadruple-Step-Ahead Hyperbolic Coordinate Rotation Digital Computer) methodology. The proposed architecture converts direct computing of function <i...

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Bibliographic Details
Main Authors: Ming Liu, Wenjia Fu, Jincheng Xia
Format: Article
Language:English
Published: MDPI AG 2021-12-01
Series:Electronics
Subjects:
floating point
<i>X<sup>Y</sup></i>-like functions
QH CORDIC
high accuracy
low latency
Online Access:https://www.mdpi.com/2079-9292/11/1/69

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https://www.mdpi.com/2079-9292/11/1/69

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