Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric
For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitan...
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| Format: | Article |
| Language: | English |
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MDPI AG
2020-11-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/11/12/1035 |
| _version_ | 1797546842685177856 |
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| author | Seungbeom Choi Seungho Song Taegyu Kim Jae Cheol Shin Jeong-Wan Jo Sung Kyu Park Yong-Hoon Kim |
| author_facet | Seungbeom Choi Seungho Song Taegyu Kim Jae Cheol Shin Jeong-Wan Jo Sung Kyu Park Yong-Hoon Kim |
| author_sort | Seungbeom Choi |
| collection | DOAJ |
| description | For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm<sup>2</sup>/Vs and on/off ratio of ~10<sup>6</sup>, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm<sup>2</sup>/Vs and an on/off ratio of >10<sup>5</sup>. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs. |
| first_indexed | 2024-03-10T14:34:57Z |
| format | Article |
| id | doaj.art-60144e2c5afd4af9abffd68e06c7e49e |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T14:34:57Z |
| publishDate | 2020-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-60144e2c5afd4af9abffd68e06c7e49e2023-11-20T22:16:49ZengMDPI AGMicromachines2072-666X2020-11-011112103510.3390/mi11121035Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate DielectricSeungbeom Choi0Seungho Song1Taegyu Kim2Jae Cheol Shin3Jeong-Wan Jo4Sung Kyu Park5Yong-Hoon Kim6School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, KoreaSchool of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, KoreaSchool of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, KoreaSchool of Electrical and Electronic Engineering, Chung-Ang University, Seoul 06980, KoreaDepartment of Electrical Engineering, University of Cambridge, Cambridge CB2 1TN, UKSchool of Electrical and Electronic Engineering, Chung-Ang University, Seoul 06980, KoreaSchool of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, KoreaFor high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm<sup>2</sup>/Vs and on/off ratio of ~10<sup>6</sup>, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm<sup>2</sup>/Vs and an on/off ratio of >10<sup>5</sup>. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs.https://www.mdpi.com/2072-666X/11/12/1035self-alignedtop-gatethin-film transistorsolution processpolymer gate dielectric |
| spellingShingle | Seungbeom Choi Seungho Song Taegyu Kim Jae Cheol Shin Jeong-Wan Jo Sung Kyu Park Yong-Hoon Kim Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric Micromachines self-aligned top-gate thin-film transistor solution process polymer gate dielectric |
| title | Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric |
| title_full | Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric |
| title_fullStr | Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric |
| title_full_unstemmed | Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric |
| title_short | Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric |
| title_sort | self aligned top gate metal oxide thin film transistors using a solution processed polymer gate dielectric |
| topic | self-aligned top-gate thin-film transistor solution process polymer gate dielectric |
| url | https://www.mdpi.com/2072-666X/11/12/1035 |
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