Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process
Abstract A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex o...
| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2023-03-01
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| Series: | Nano Convergence |
| Subjects: | |
| Online Access: | https://doi.org/10.1186/s40580-023-00362-w |
| _version_ | 1797863872222199808 |
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| author | Yongsu Lee Heejin Kwon Seung-Mo Kim Ho-In Lee Kiyung Kim Hae-Won Lee So-Young Kim Hyeon Jun Hwang Byoung Hun Lee |
| author_facet | Yongsu Lee Heejin Kwon Seung-Mo Kim Ho-In Lee Kiyung Kim Hae-Won Lee So-Young Kim Hyeon Jun Hwang Byoung Hun Lee |
| author_sort | Yongsu Lee |
| collection | DOAJ |
| description | Abstract A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit. |
| first_indexed | 2024-04-09T22:42:36Z |
| format | Article |
| id | doaj.art-606aac6476ab47699952f522ebeed8dd |
| institution | Directory Open Access Journal |
| issn | 2196-5404 |
| language | English |
| last_indexed | 2024-04-09T22:42:36Z |
| publishDate | 2023-03-01 |
| publisher | SpringerOpen |
| record_format | Article |
| series | Nano Convergence |
| spelling | doaj.art-606aac6476ab47699952f522ebeed8dd2023-03-22T12:02:55ZengSpringerOpenNano Convergence2196-54042023-03-011011910.1186/s40580-023-00362-wDemonstration of p-type stack-channel ternary logic device using scalable DNTT patterning processYongsu Lee0Heejin Kwon1Seung-Mo Kim2Ho-In Lee3Kiyung Kim4Hae-Won Lee5So-Young Kim6Hyeon Jun Hwang7Byoung Hun Lee8Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and TechnologyAbstract A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit.https://doi.org/10.1186/s40580-023-00362-wOrganic semiconductorPhotolithographyTernary logicStack-channelZero differential conductance |
| spellingShingle | Yongsu Lee Heejin Kwon Seung-Mo Kim Ho-In Lee Kiyung Kim Hae-Won Lee So-Young Kim Hyeon Jun Hwang Byoung Hun Lee Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process Nano Convergence Organic semiconductor Photolithography Ternary logic Stack-channel Zero differential conductance |
| title | Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process |
| title_full | Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process |
| title_fullStr | Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process |
| title_full_unstemmed | Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process |
| title_short | Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process |
| title_sort | demonstration of p type stack channel ternary logic device using scalable dntt patterning process |
| topic | Organic semiconductor Photolithography Ternary logic Stack-channel Zero differential conductance |
| url | https://doi.org/10.1186/s40580-023-00362-w |
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