Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM

Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM

In this article, a honeycomb vertical surrounding gate access transistor array scheme is proposed to further decrease the DRAM cell area with aggressively shrink bit line (BL) pitch and word line (WL) pitch adopting the ZigZag BL and WL air gap. To verify the process feasibility, process flow emulat...

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Bibliographic Details
Main Authors: Wenqi Wang, Sang Don Yi, Fu Li, Qingchen Cao, Jiangliu Shi, Bok-Moon Kang, Meichen Jin, Chang Liu, Zhenhua Wu, Guilei Wang, Chao Zhao
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Vertical surrounding gate transistor (VSGT)
dynamic random-access memory (DRAM)
parasitic capacitance
optical proximity correction (OPC)
area scaling
power saving
Online Access:https://ieeexplore.ieee.org/document/10483008/

Internet

https://ieeexplore.ieee.org/document/10483008/

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