A high‐performance full swing 1‐bit hybrid full adder cell
Abstract This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2022-05-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12097 |
| _version_ | 1827077569161199616 |
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| author | Shahbaz Hussain Mehedi Hasan Gazal Agrawal Mohd Hasan |
| author_facet | Shahbaz Hussain Mehedi Hasan Gazal Agrawal Mohd Hasan |
| author_sort | Shahbaz Hussain |
| collection | DOAJ |
| description | Abstract This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors. |
| first_indexed | 2024-03-09T09:00:10Z |
| format | Article |
| id | doaj.art-62a191b85e8e4efaab9847a39ab48253 |
| institution | Directory Open Access Journal |
| issn | 1751-858X 1751-8598 |
| language | English |
| last_indexed | 2025-03-20T02:15:51Z |
| publishDate | 2022-05-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj.art-62a191b85e8e4efaab9847a39ab482532024-10-03T07:51:12ZengHindawi-IETIET Circuits, Devices and Systems1751-858X1751-85982022-05-0116321021710.1049/cds2.12097A high‐performance full swing 1‐bit hybrid full adder cellShahbaz Hussain0Mehedi Hasan1Gazal Agrawal2Mohd Hasan3Department of Electronics Engineering Aligarh Muslim University Aligarh Uttar Pradesh IndiaDepartment of Electrical and Computer Engineering North South University Dhaka BangladeshDepartment of Electronics Engineering Aligarh Muslim University Aligarh Uttar Pradesh IndiaDepartment of Electronics Engineering Aligarh Muslim University Aligarh Uttar Pradesh IndiaAbstract This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.https://doi.org/10.1049/cds2.12097logic gateslogic designadderscarry logicSPICEperformance evaluation |
| spellingShingle | Shahbaz Hussain Mehedi Hasan Gazal Agrawal Mohd Hasan A high‐performance full swing 1‐bit hybrid full adder cell IET Circuits, Devices and Systems logic gates logic design adders carry logic SPICE performance evaluation |
| title | A high‐performance full swing 1‐bit hybrid full adder cell |
| title_full | A high‐performance full swing 1‐bit hybrid full adder cell |
| title_fullStr | A high‐performance full swing 1‐bit hybrid full adder cell |
| title_full_unstemmed | A high‐performance full swing 1‐bit hybrid full adder cell |
| title_short | A high‐performance full swing 1‐bit hybrid full adder cell |
| title_sort | high performance full swing 1 bit hybrid full adder cell |
| topic | logic gates logic design adders carry logic SPICE performance evaluation |
| url | https://doi.org/10.1049/cds2.12097 |
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