4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si<sub>0.7</sub>Ge<sub>0.3</sub> channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si<sub>...

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Bibliographic Details
Main Authors: Xiaohong Cheng, Yongliang Li, Fei Zhao, Anlan Chen, Haoyan Liu, Chun Li, Qingzhu Zhang, Huaxiang Yin, Jun Luo, Wenwu Wang
Format: Article
Language:English
Published: MDPI AG 2022-03-01
Series:Nanomaterials
Subjects:
SiGe channel
gate-all-around
release
silicide
Online Access:https://www.mdpi.com/2079-4991/12/5/889

Internet

https://www.mdpi.com/2079-4991/12/5/889

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