Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration

Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and othe...

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Bibliographic Details
Main Authors: Xuyan Chen, Zhiming Chen, Lei Xiao, Yigang Hao, Han Wang, Yingtao Ding, Ziyue Zhang
Format: Article
Language:English
Published: MDPI AG 2022-07-01
Series:Micromachines
Subjects:
three-dimensional (3D) integration
high aspect ratio (HAR) through-silicon vias (TSVs)
polyimide (PI) liner
Cu seed layer
redistribution layers (RDLs)
S-parameters
Online Access:https://www.mdpi.com/2072-666X/13/7/1147

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https://www.mdpi.com/2072-666X/13/7/1147

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