Hardware Implementation of Improved Banker’s Fixed-Point Rounding Algorithm

Hardware Implementation of Improved Banker’s Fixed-Point Rounding Algorithm

In recent years, FPGA-based convolutional neural networks (CNNs) accelerator has received tremendous research interest, especially in fields such as autonomous driving and robotics. For the purpose of accelerating convolution computations, Winograd fast convolution algorithm is frequently employed....

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Hlavní autoři: Peng Yun, Wang Yubing, Zhang Yingxu, Liang Lei, Zhang Jun, Zhang Jianwei, Qin Li, Wang Lijun
Médium: Článek
Jazyk:English
Vydáno: IEEE 2025-01-01
Edice:IEEE Access
Témata:
Banker’s rounding
FPGA
fixed-point arithmetic
convolution
On-line přístup:https://ieeexplore.ieee.org/document/10892116/

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https://ieeexplore.ieee.org/document/10892116/

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