Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes
In this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10254548/ |