Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes
In this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10254548/ |
| _version_ | 1797665408247922688 |
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| author | Swapna Sarker Abhishek Kumar Mohammad Ehteshamuddin Avirup Dasgupta |
| author_facet | Swapna Sarker Abhishek Kumar Mohammad Ehteshamuddin Avirup Dasgupta |
| author_sort | Swapna Sarker |
| collection | DOAJ |
| description | In this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and Schwarz Christoffel transforms as well as elliptic integral methods are used to model the perpendicular capacitance as well as coplanar plate capacitance. We have also used fundamental capacitance modeling to calculate the corner capacitance. The validity of the proposed model is calibrated and verified with the 3D TCAD simulations. Evaluation is also done of how different device physical parameters affect the total parasitic capacitance. The results demonstrate that the proposed model is capable of accurately estimating the parasitic capacitance of the GAAFET device. The proposed model is also implemented in the BSIM-CMG framework to verify the model’s accuracy and application of it in the circuit simulation. |
| first_indexed | 2024-03-11T19:44:28Z |
| format | Article |
| id | doaj.art-64aa1655f6624202a8b21bdf7d83770d |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-03-11T19:44:28Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-64aa1655f6624202a8b21bdf7d83770d2023-10-05T23:00:25ZengIEEEIEEE Journal of the Electron Devices Society2168-67342023-01-011151051710.1109/JEDS.2023.331683510254548Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology NodesSwapna Sarker0https://orcid.org/0000-0003-0830-0318Abhishek Kumar1https://orcid.org/0000-0002-9355-3354Mohammad Ehteshamuddin2https://orcid.org/0000-0002-9235-1355Avirup Dasgupta3https://orcid.org/0000-0001-7477-0436Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, IndiaDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, IndiaDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, IndiaDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, IndiaIn this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and Schwarz Christoffel transforms as well as elliptic integral methods are used to model the perpendicular capacitance as well as coplanar plate capacitance. We have also used fundamental capacitance modeling to calculate the corner capacitance. The validity of the proposed model is calibrated and verified with the 3D TCAD simulations. Evaluation is also done of how different device physical parameters affect the total parasitic capacitance. The results demonstrate that the proposed model is capable of accurately estimating the parasitic capacitance of the GAAFET device. The proposed model is also implemented in the BSIM-CMG framework to verify the model’s accuracy and application of it in the circuit simulation.https://ieeexplore.ieee.org/document/10254548/GAAFETparasitic capacitanceconformal mappingBSIM-CMG |
| spellingShingle | Swapna Sarker Abhishek Kumar Mohammad Ehteshamuddin Avirup Dasgupta Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes IEEE Journal of the Electron Devices Society GAAFET parasitic capacitance conformal mapping BSIM-CMG |
| title | Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes |
| title_full | Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes |
| title_fullStr | Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes |
| title_full_unstemmed | Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes |
| title_short | Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes |
| title_sort | compact modeling of parasitic capacitances in gaafets for advanced technology nodes |
| topic | GAAFET parasitic capacitance conformal mapping BSIM-CMG |
| url | https://ieeexplore.ieee.org/document/10254548/ |
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