Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel counters (GPCs) were synthesized on FPGAs to...

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Bibliographic Details
Main Authors: Yuelai Yuan, Le Tu, Kan Huang, Xiaoqiang Zhang, Tiejun Zhang, Dihu Chen, Zixin Wang
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Generalized parallel counter (GPC)
compressor tree
integer linear programming (ILP)
field programmable gate array (FPGA)
Online Access:https://ieeexplore.ieee.org/document/8843959/

Internet

https://ieeexplore.ieee.org/document/8843959/

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