Design Methodologies for Low-Jitter CMOS Clock Distribution

Design Methodologies for Low-Jitter CMOS Clock Distribution

Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, it is important to understand their limitations and explore de...

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Bibliographic Details
Main Authors: Xunjun Mo, Jiaqi Wu, Nijwm Wary, Tony Chan Carusone
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Open Journal of the Solid-State Circuits Society
Subjects:
Clock distribution
clock jitter
jitter amplification
jitter generation
power supply induced jitter
Online Access:https://ieeexplore.ieee.org/document/9559395/

Internet

https://ieeexplore.ieee.org/document/9559395/

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