Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes
Abstract Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward tr...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Springer
2021-04-01
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| Series: | SN Applied Sciences |
| Subjects: | |
| Online Access: | https://doi.org/10.1007/s42452-021-04539-y |