A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification
In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of ari...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-12-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/12/1/2 |
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| author | Daniel Reiser Peter Reichel Stefan Pechmann Maen Mallah Maximilian Oppelt Amelie Hagelauer Marco Breiling Dietmar Fey Marc Reichenbach |
| author_facet | Daniel Reiser Peter Reichel Stefan Pechmann Maen Mallah Maximilian Oppelt Amelie Hagelauer Marco Breiling Dietmar Fey Marc Reichenbach |
| author_sort | Daniel Reiser |
| collection | DOAJ |
| description | In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved. |
| first_indexed | 2024-03-09T19:35:35Z |
| format | Article |
| id | doaj.art-68ac0723146c4766a5980d12aa86f3f3 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-03-09T19:35:35Z |
| publishDate | 2021-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-68ac0723146c4766a5980d12aa86f3f32023-11-24T01:55:44ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682021-12-01121210.3390/jlpea12010002A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series ClassificationDaniel Reiser0Peter Reichel1Stefan Pechmann2Maen Mallah3Maximilian Oppelt4Amelie Hagelauer5Marco Breiling6Dietmar Fey7Marc Reichenbach8Chair of Computer Science 3 (Computer Architecture), Friedrich-Alexander University Erlangen-Nuernberg, 91058 Erlangen, GermanyFraunhofer Institute for Integrated Circuits (IIS), Division Engineering of Adaptive Systems EAS, 01187 Dresden, GermanyChair of Micro and Nanosystems Technology, Technical University of Munich, 80333 Munich, GermanyFraunhofer Institute for Integrated Circuits (IIS), 91058 Erlangen, GermanyFraunhofer Institute for Integrated Circuits (IIS), 91058 Erlangen, GermanyChair of Micro and Nanosystems Technology, Technical University of Munich, 80333 Munich, GermanyFraunhofer Institute for Integrated Circuits (IIS), 91058 Erlangen, GermanyChair of Computer Science 3 (Computer Architecture), Friedrich-Alexander University Erlangen-Nuernberg, 91058 Erlangen, GermanyChair of Computer Engineering, Brandenburg University of Technology (B-TU), 03046 Cottbus, GermanyIn embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.https://www.mdpi.com/2079-9268/12/1/2hardware architectureneural networksnon-volatile memorywearable AIRRAM |
| spellingShingle | Daniel Reiser Peter Reichel Stefan Pechmann Maen Mallah Maximilian Oppelt Amelie Hagelauer Marco Breiling Dietmar Fey Marc Reichenbach A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification Journal of Low Power Electronics and Applications hardware architecture neural networks non-volatile memory wearable AI RRAM |
| title | A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification |
| title_full | A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification |
| title_fullStr | A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification |
| title_full_unstemmed | A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification |
| title_short | A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification |
| title_sort | framework for ultra low power hardware accelerators using nns for embedded time series classification |
| topic | hardware architecture neural networks non-volatile memory wearable AI RRAM |
| url | https://www.mdpi.com/2079-9268/12/1/2 |
| work_keys_str_mv | AT danielreiser aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT peterreichel aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT stefanpechmann aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT maenmallah aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT maximilianoppelt aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT ameliehagelauer aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT marcobreiling aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT dietmarfey aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT marcreichenbach aframeworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT danielreiser frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT peterreichel frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT stefanpechmann frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT maenmallah frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT maximilianoppelt frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT ameliehagelauer frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT marcobreiling frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT dietmarfey frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification AT marcreichenbach frameworkforultralowpowerhardwareacceleratorsusingnnsforembeddedtimeseriesclassification |