Low-Complexity Architecture for High-Speed 50G-PON LDPC Decoder

Low-Complexity Architecture for High-Speed 50G-PON LDPC Decoder

We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competi...

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Detalhes bibliográficos
Principais autores: Kon-Woo Kwon, Kwangok Kim, Kyeonghwan Doo, Hwanseok Chung, Jeong Woo Lee
Formato: Artigo
Idioma:English
Publicado em: IEEE 2025-01-01
coleção:IEEE Access
Assuntos:
50G-PON
LDPC decoder
high throughput
low complexity
architecture
FPGA
Acesso em linha:https://ieeexplore.ieee.org/document/10879318/

Internet

https://ieeexplore.ieee.org/document/10879318/

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