Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory

Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory

When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics. However, only a limited amount of data can be used...

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Bibliographic Details
Main Authors: Yohan Kim, Soyoung Kim
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Acceleration
artificial neural network
bit error rate
circuit simulation
compact model
GIDL-assisted erase
Online Access:https://ieeexplore.ieee.org/document/10233846/

Internet

https://ieeexplore.ieee.org/document/10233846/

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