Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscrip...

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Bibliographic Details
Main Authors: Seyedehsomayeh Hatefinasab, Akiko Ohata, Alfonso Salinas, Encarnacion Castillo, Noel Rodriguez
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Power-delay product (PDP)
soft errors (SE)
single event upset (SEU)
high impedance state (HIS)
single event transient (SET)
dual interlocked storage cell (DICE)
Online Access:https://ieeexplore.ieee.org/document/9737482/

Internet

https://ieeexplore.ieee.org/document/9737482/

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