DIRECT TUNNELLING AND MOSFET BORDER TRAPS
The border traps, in particular slow border traps, are being investigated in metal-oxide-semiconductor structures, utilizing n-channel MOSFET as a test sample. The industrial process technology of test samples manufacturing is described. The automated experimental setup is discussed, the implementat...
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Science and Innovation Center Publishing House
2015-09-01
|
| Series: | International Journal of Advanced Studies |
| Subjects: | |
| Online Access: | http://journal-s.org/index.php/ijas/article/view/8532 |
| Summary: | The border traps, in particular slow border traps, are being investigated in metal-oxide-semiconductor structures, utilizing n-channel MOSFET as a test sample. The industrial process technology of test samples manufacturing is described. The automated experimental setup is discussed, the implementation of the experimental setup had made it possible to complete the entire set of measurements. The schematic diagram of automated experimental setup is shown. The charging time characteristic of the ID-VG shift reveals that the charging process is a direct tunnelling process and highly bias dependent. |
|---|---|
| ISSN: | 2328-1391 2227-930X |