Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify t...

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Bibliographic Details
Main Authors: Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Circuit faults
digital integrated circuits
fault detection
fault tolerant computing
field programmable gate arrays
microprocessors
Online Access:https://ieeexplore.ieee.org/document/9968000/

Internet

https://ieeexplore.ieee.org/document/9968000/

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