A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enabl...

Full description

Bibliographic Details
Main Authors: Hyeonsik Kim, Soohoon Lee, Jintae Kim
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Analog-to-digital converter (ADC)
pipelined successive approximation resister (SAR)
dynamic amplifier
replica-biasing
Online Access:https://ieeexplore.ieee.org/document/10052667/

Internet

https://ieeexplore.ieee.org/document/10052667/

Similar Items