| Summary: | To give consideration to both chip density and device performance, an In<sub>0.53</sub>Ga<sub>0.47</sub>As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P<sup>+</sup>-pocket and an In<sub>0.52</sub>Al<sub>0.48</sub>As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P<sup>+</sup>-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In<sub>0.52</sub>Al<sub>0.48</sub>As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P<sup>+</sup>-pocket as well as the length and width of the In<sub>0.52</sub>Al<sub>0.48</sub>As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10<sup>−19</sup> A/μm, on-state current of 1.04 × 10<sup>−4</sup> A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.
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