Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance

Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance

In many scenarios, edge devices perform computations for applications such as target detection and tracking, multimodal sensor fusion, low-light image enhancement, and image segmentation. There is an increasing trend of deploying and running multiple different network models on one hardware platform...

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Bibliographic Details
Main Authors: Haoran Tong, Ke Han, Si Han, Yingqi Luo
Format: Article
Language:English
Published: MDPI AG 2024-02-01
Series:Electronics
Subjects:
hardware accelerator
convolutional neural network
depthwise separable convolution
deconvolution
dynamically reconfigurable
on-chip computing scheme
Online Access:https://www.mdpi.com/2079-9292/13/4/761

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https://www.mdpi.com/2079-9292/13/4/761

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