Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance
In many scenarios, edge devices perform computations for applications such as target detection and tracking, multimodal sensor fusion, low-light image enhancement, and image segmentation. There is an increasing trend of deploying and running multiple different network models on one hardware platform...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2024-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/13/4/761 |
| _version_ | 1797298350996848640 |
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| author | Haoran Tong Ke Han Si Han Yingqi Luo |
| author_facet | Haoran Tong Ke Han Si Han Yingqi Luo |
| author_sort | Haoran Tong |
| collection | DOAJ |
| description | In many scenarios, edge devices perform computations for applications such as target detection and tracking, multimodal sensor fusion, low-light image enhancement, and image segmentation. There is an increasing trend of deploying and running multiple different network models on one hardware platform, but there is a lack of generic acceleration architectures that support standard convolution (CONV), depthwise separable CONV, and deconvolution (DeCONV) layers in such complex scenarios. In response, this paper proposes a more versatile dynamically reconfigurable CNN accelerator with a highly unified computing scheme. The proposed design, which is compatible with standard CNNs, lightweight CNNs, and CNNs with DeCONV layers, further improves the resource utilization and reduces the gap of efficiency when deploying different models. Thus, the hardware balance during the alternating execution of multiple models is enhanced. Compared to a state-of-the-art CNN accelerator, Xilinx DPU B4096, our optimized architecture achieves resource utilization improvements of 1.08× for VGG16 and 1.77× for MobileNetV1 in inference tasks on the Xilinx ZCU102 platform. The resource utilization and efficiency degradation between these two models are reduced to 59.6% and 63.7%, respectively. Furthermore, the proposed architecture can properly run DeCONV layers and demonstrates good performance. |
| first_indexed | 2024-03-07T22:34:33Z |
| format | Article |
| id | doaj.art-7204ea38908a49bca4d8c9235fc89a1f |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-07T22:34:33Z |
| publishDate | 2024-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-7204ea38908a49bca4d8c9235fc89a1f2024-02-23T15:14:51ZengMDPI AGElectronics2079-92922024-02-0113476110.3390/electronics13040761Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal BalanceHaoran Tong0Ke Han1Si Han2Yingqi Luo3School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaSchool of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaSchool of Information Management for Laws, China University for Political Science and Law, Beijing 100091, ChinaSchool of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaIn many scenarios, edge devices perform computations for applications such as target detection and tracking, multimodal sensor fusion, low-light image enhancement, and image segmentation. There is an increasing trend of deploying and running multiple different network models on one hardware platform, but there is a lack of generic acceleration architectures that support standard convolution (CONV), depthwise separable CONV, and deconvolution (DeCONV) layers in such complex scenarios. In response, this paper proposes a more versatile dynamically reconfigurable CNN accelerator with a highly unified computing scheme. The proposed design, which is compatible with standard CNNs, lightweight CNNs, and CNNs with DeCONV layers, further improves the resource utilization and reduces the gap of efficiency when deploying different models. Thus, the hardware balance during the alternating execution of multiple models is enhanced. Compared to a state-of-the-art CNN accelerator, Xilinx DPU B4096, our optimized architecture achieves resource utilization improvements of 1.08× for VGG16 and 1.77× for MobileNetV1 in inference tasks on the Xilinx ZCU102 platform. The resource utilization and efficiency degradation between these two models are reduced to 59.6% and 63.7%, respectively. Furthermore, the proposed architecture can properly run DeCONV layers and demonstrates good performance.https://www.mdpi.com/2079-9292/13/4/761hardware acceleratorconvolutional neural networkdepthwise separable convolutiondeconvolutiondynamically reconfigurableon-chip computing scheme |
| spellingShingle | Haoran Tong Ke Han Si Han Yingqi Luo Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance Electronics hardware accelerator convolutional neural network depthwise separable convolution deconvolution dynamically reconfigurable on-chip computing scheme |
| title | Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance |
| title_full | Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance |
| title_fullStr | Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance |
| title_full_unstemmed | Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance |
| title_short | Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance |
| title_sort | design of a generic dynamically reconfigurable convolutional neural network accelerator with optimal balance |
| topic | hardware accelerator convolutional neural network depthwise separable convolution deconvolution dynamically reconfigurable on-chip computing scheme |
| url | https://www.mdpi.com/2079-9292/13/4/761 |
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