Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space,...

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Bibliographic Details
Main Authors: Xin Wei, Yi Z Xie, Yu Xie, He Chen
Format: Article
Language:English
Published: Wiley 2019-10-01
Series:The Journal of Engineering
Subjects:
field programmable gate arrays
fault tolerant computing
fast fourier transforms
redundancy
radiation hardening (electronics)
microprocessor chips
reconfiguration time
multipath delay feedback fft controller
dynamic partial reconfiguration scheme
fault-tolerant fft processor
field programmable gate array
logical resources
storage resources
dynamic partial reconfiguration technique
fast fourier transform fft processor
novel fpga scrubbing framework
high-energy particles
triple modular redundancy scheme
dpr controller
blind scrubbing
xilinx prc ip
single event upset
Online Access:https://digital-library.theiet.org/content/journals/10.1049/joe.2019.0353

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https://digital-library.theiet.org/content/journals/10.1049/joe.2019.0353

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