A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory
In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and v...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-07-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/13/7/1070 |
| _version_ | 1797416938681401344 |
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| author | Hyunwoong Kim Seonghi Lee Kyunghwan Song Yujun Shin Dongyrul Park Jongcheol Park Jaeyong Cho Seungyoung Ahn |
| author_facet | Hyunwoong Kim Seonghi Lee Kyunghwan Song Yujun Shin Dongyrul Park Jongcheol Park Jaeyong Cho Seungyoung Ahn |
| author_sort | Hyunwoong Kim |
| collection | DOAJ |
| description | In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel. |
| first_indexed | 2024-03-09T06:11:36Z |
| format | Article |
| id | doaj.art-72be08c71b3d418b8a0b673eb3e6d93d |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-09T06:11:36Z |
| publishDate | 2022-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-72be08c71b3d418b8a0b673eb3e6d93d2023-12-03T11:57:48ZengMDPI AGMicromachines2072-666X2022-07-01137107010.3390/mi13071070A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth MemoryHyunwoong Kim0Seonghi Lee1Kyunghwan Song2Yujun Shin3Dongyrul Park4Jongcheol Park5Jaeyong Cho6Seungyoung Ahn7Korea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaKorea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaKorea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaKorea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaKorea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaDepartment of System IC Development, National NanoFab Center, Daejeon 34141, KoreaHuwin, Seongnam 13558, KoreaKorea Advanced Institute of Science and Technology, Cho Chun Shik Graduate School of Mobility, Deajeon 34051, KoreaIn this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.https://www.mdpi.com/2072-666X/13/7/1070broadside structurefar-end crosstalkimpedanceinterposer channelsilicon interposervertical tabbed via |
| spellingShingle | Hyunwoong Kim Seonghi Lee Kyunghwan Song Yujun Shin Dongyrul Park Jongcheol Park Jaeyong Cho Seungyoung Ahn A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory Micromachines broadside structure far-end crosstalk impedance interposer channel silicon interposer vertical tabbed via |
| title | A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory |
| title_full | A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory |
| title_fullStr | A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory |
| title_full_unstemmed | A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory |
| title_short | A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory |
| title_sort | novel interposer channel structure with vertical tabbed vias to reduce far end crosstalk for next generation high bandwidth memory |
| topic | broadside structure far-end crosstalk impedance interposer channel silicon interposer vertical tabbed via |
| url | https://www.mdpi.com/2072-666X/13/7/1070 |
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