A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

Based on a self-biased architecture, this paper presents a novel adaptive fast-locking, wide operating range and low-jitter phase-locked loop (PLL). A current injection and adaptive bandwidth technology with minimum area overhead is employed to speed up the loop equilibrium acquisition process, with...

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Bibliographic Details
Main Authors: Binghui Wang, Haigang Yang, Yiping Jia
Format: Article
Language:English
Published: MDPI AG 2022-06-01
Series:Electronics
Subjects:
self-biased PLL
adaptive fast-locking PLL
start-up circuit
current injection
Online Access:https://www.mdpi.com/2079-9292/11/13/1954

Internet

https://www.mdpi.com/2079-9292/11/13/1954

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