Time efficient signed Vedic multiplier using redundant binary representation

Time efficient signed Vedic multiplier using redundant binary representation

This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. This is the first ever effort towards extension of Vedic algorithms to the signed numbers. The proposed multiplier architecture solves the carry pr...

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Bibliographic Details
Main Authors: Ranjan Kumar Barik, Manoranjan Pradhan, Rutuparna Panda
Format: Article
Language:English
Published: Wiley 2017-03-01
Series:The Journal of Engineering
Subjects:
multiplying circuits
field programmable gate arrays
FPGA devices
Xilinx ISE 14.4
carry free addition
carry propagation issue
signed numbers
Vedic algorithms
UT sutra
Urdhva Tiryagbhyam sutra
RB representation
redundant binary representation
SVM architecture
time efficient signed Vedic multiplier
Online Access:http://digital-library.theiet.org/content/journals/10.1049/joe.2016.0376

Internet

http://digital-library.theiet.org/content/journals/10.1049/joe.2016.0376

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