Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as...

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Bibliographic Details
Main Authors: Yejin Ha, Hyungsoon Shin, Wookyung Sun, Jisun Park
Format: Article
Language:English
Published: MDPI AG 2021-10-01
Series:Micromachines
Subjects:
capacitorless one-transistor dynamic random-access memory
1T-DRAM
polysilicon
array
circuit
memory
Online Access:https://www.mdpi.com/2072-666X/12/10/1209

Internet

https://www.mdpi.com/2072-666X/12/10/1209

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