Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits
The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (V<sub>DD</sub>) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9555812/ |
| _version_ | 1831761661315252224 |
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| author | Yi-Chun Huang Ming-Dou Ker |
| author_facet | Yi-Chun Huang Ming-Dou Ker |
| author_sort | Yi-Chun Huang |
| collection | DOAJ |
| description | The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (V<sub>DD</sub>) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> CMOS technology. |
| first_indexed | 2024-12-22T04:52:32Z |
| format | Article |
| id | doaj.art-7b0a7c7f13b54e98bd1720c7eb3bfb37 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-22T04:52:32Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-7b0a7c7f13b54e98bd1720c7eb3bfb372022-12-21T18:38:27ZengIEEEIEEE Journal of the Electron Devices Society2168-67342021-01-01988189010.1109/JEDS.2021.31169619555812Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated CircuitsYi-Chun Huang0https://orcid.org/0000-0002-4909-5149Ming-Dou Ker1https://orcid.org/0000-0003-3622-181XInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanThe integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (V<sub>DD</sub>) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> CMOS technology.https://ieeexplore.ieee.org/document/9555812/Power line noisetransient/switching noiseparasitic inductancedecoupling capacitorcharged-device model (CDM)electrostatic discharge (ESD) |
| spellingShingle | Yi-Chun Huang Ming-Dou Ker Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits IEEE Journal of the Electron Devices Society Power line noise transient/switching noise parasitic inductance decoupling capacitor charged-device model (CDM) electrostatic discharge (ESD) |
| title | Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits |
| title_full | Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits |
| title_fullStr | Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits |
| title_full_unstemmed | Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits |
| title_short | Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits |
| title_sort | study on cdm esd robustness among on chip decoupling capacitors in cmos integrated circuits |
| topic | Power line noise transient/switching noise parasitic inductance decoupling capacitor charged-device model (CDM) electrostatic discharge (ESD) |
| url | https://ieeexplore.ieee.org/document/9555812/ |
| work_keys_str_mv | AT yichunhuang studyoncdmesdrobustnessamongonchipdecouplingcapacitorsincmosintegratedcircuits AT mingdouker studyoncdmesdrobustnessamongonchipdecouplingcapacitorsincmosintegratedcircuits |