A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

Radiation can affect the correct behavior of an electronic device. Hence, the microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is used for mitigating various kinds of faults in an electronic circuit. Although TMR provides an excellent level...

Full description

Bibliographic Details
Main Authors:	Satyam Shukla, Kailash Chandra Ray
Format:	Article
Language:	English
Published:	IEEE 2022-01-01
Series:	IEEE Access
Subjects:	Reconfigurable VLSI architectures fault-tolerant processor FPGA implementation RISC-V ISA single event upset
Online Access:	https://ieeexplore.ieee.org/document/9761919/

Similar Items

An Educational RISC-V-Based 16-Bit Processor
by: Jecel Mattos de Assumpção, et al.
Published: (2024-11-01)

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
by: Görkem Nişancı, et al.
Published: (2022-08-01)

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator
by: Eunjin Choi, et al.
Published: (2024-12-01)

A novel method for on-chip debugging based on RISC-V processor
by: Gao Shan, et al.
Published: (2022-01-01)

Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V
by: Seonghwan Park, et al.
Published: (2022-02-01)

Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection
by: Seyed Kian Mousavikia, et al.
Published: (2022-01-01)

Optimized Implementation of SM4 on AVR Microcontrollers, RISC-V Processors, and ARM Processors
by: Hyeokdong Kwon, et al.
Published: (2022-01-01)

RISC-V processor FPGA implementation
by: Tey, Jing Kai
Published: (2024)

A Programmable Crypto-Processor for National Institute of Standards and Technology Post-Quantum Cryptography Standardization Based on the RISC-V Architecture
by: Jihye Lee, et al.
Published: (2023-11-01)

Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
by: Zhiwei Jin, et al.
Published: (2025-01-01)

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection
by: Francesco Vigli, et al.
Published: (2024-01-01)

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors
by: Ahmed Kamaleldin, et al.
Published: (2022-01-01)

CORDIC Hardware Acceleration Using DMA-Based ISA Extension
by: Erez Manor, et al.
Published: (2022-01-01)

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems
by: Marc Reichenbach, et al.
Published: (2021-01-01)

FPGA-based prototyping of IEEE 802.11a base band processor
by: Dramićanin Dejan M., et al.
Published: (2004-01-01)

NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V
by: Hakan Uzuner, et al.
Published: (2024-02-01)

An ultra-low-power processor pipeline-structure
by: Deng Tianchuan, et al.
Published: (2019-06-01)

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA
by: Khai-Minh Ma, et al.
Published: (2023-05-01)

RISC Conversions for LNS Arithmetic in Embedded Systems
by: Peter Drahoš, et al.
Published: (2020-07-01)

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization
by: Shanwen Wu, et al.
Published: (2024-01-01)

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor
by: Donald E. Owen, et al.
Published: (2022-08-01)

Design of the 16 - bit pipeline risc processor in FPGA /
by: 226231 Loo, Ai Choo, et al.
Published: (2005)

Design of the distributed Cache for reconfigurable array processor
by: Jiang Lin, et al.
Published: (2018-12-01)

In-Pipeline Processor Protection against Soft Errors
by: Ján Mach, et al.
Published: (2023-05-01)

Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA
by: Xin Wei, et al.
Published: (2019-10-01)

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
by: Idris O. Somoye, et al.
Published: (2024-04-01)

A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems
by: Tanougast Camel, et al.
Published: (2003-01-01)

Development of single board computer based on 32-bit 5-stage pipeline RISC processor /
by: Koay Boon Wooi, 1983-, et al.
Published: (2009)

FPGA and digital SOIC SET’s control under heavy ion and proton irradiation
by: Georgii Sergeevich Sorokoumov, et al.
Published: (2016-10-01)

Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers
by: Peter Jamieson, et al.
Published: (2022-08-01)

The Nontrivial Problem of Matching in Redundant Digital Systems
by: SZÁSZ Csaba, et al.
Published: (2019-05-01)

Development of single board computer based on 32-bit 5-stage pipeline RISC processor [electronic resource /
by: Koay Boon Wooi, 1983-, et al.
Published: (2009)

Reconfigurable Hardware Technology Application in Servo Control Systems
by: SZÁSZ Csaba
Published: (2024-05-01)

Implementation of Multi-Core Processor Based on PLASMA (most MIPS I) IP Core
by: Bojan Gruevski, et al.
Published: (2014-03-01)

FPGA Implementation of Mean – Max Membership basedDefuzzifier Unit
by: Asim M. Murshid
Published: (2015-09-01)

FAC-V: An FPGA-Based AES Coprocessor for RISC-V
by: Tiago Gomes, et al.
Published: (2022-09-01)

Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors
by: Youngbeom Kim, et al.
Published: (2022-01-01)

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators
by: Ahmed Kamaleldin, et al.
Published: (2020-01-01)

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool
by: Cosmin-Andrei Popovici, et al.
Published: (2023-01-01)

RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO<sub>2</sub> Concentration Sensing
by: Ricardo Núñez-Prieto, et al.
Published: (2023-07-01)