Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, n...

Full description

Bibliographic Details
Main Authors: Yage Zhao, Zhongshan Xu, Huawei Tang, Yusi Zhao, Peishun Tang, Rongzheng Ding, Xiaona Zhu, David Wei Zhang, Shaofeng Yu
Format: Article
Language:English
Published: MDPI AG 2024-01-01
Series:Micromachines
Subjects:
gate-all-around (GAA) Nanosheet FETs (NSFETs)
compact model
artificial neural network (ANN)
TCAD simulation
Online Access:https://www.mdpi.com/2072-666X/15/2/218

Internet

https://www.mdpi.com/2072-666X/15/2/218

Similar Items