Low-power design for full adder circuits(低功耗全加器的电路设计)
在对现有全加器电路研究分析的基础上,提出了基于传输管逻辑的低功耗全加器.所建议的电路采用对称结构平衡电路延迟,削减了毛刺,降低了功耗.采用TSMC 0.24 µm CMOS工艺器件参数情况下,对所设计的低功耗全加器进行PSPICE模拟.模拟结果表明,在3.3 V和1.8 V电源电压下,与已发表的全加器相比,所建议的全加器电路功耗改进可分别高达58.3%和60.8%....
Main Authors: | , |
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Format: | Article |
Language: | zho |
Published: |
Zhejiang University Press
2008-09-01
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Series: | Zhejiang Daxue xuebao. Lixue ban |
Subjects: | |
Online Access: | https://doi.org/10.3785/j.issn.1008-9497.2008.05.013 |