An Optimization Framework for the Design of High-Speed PCB VIAs
Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types o...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/3/475 |
| _version_ | 1797488320974946304 |
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| author | Gianfranco Avitabile Antonello Florio Vito Leonardo Gallo Alessandro Pali Lorenzo Forni |
| author_facet | Gianfranco Avitabile Antonello Florio Vito Leonardo Gallo Alessandro Pali Lorenzo Forni |
| author_sort | Gianfranco Avitabile |
| collection | DOAJ |
| description | Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results. |
| first_indexed | 2024-03-10T00:00:27Z |
| format | Article |
| id | doaj.art-7bc48d81fc8e4530bea11c618d8b002b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T00:00:27Z |
| publishDate | 2022-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-7bc48d81fc8e4530bea11c618d8b002b2023-11-23T16:17:32ZengMDPI AGElectronics2079-92922022-02-0111347510.3390/electronics11030475An Optimization Framework for the Design of High-Speed PCB VIAsGianfranco Avitabile0Antonello Florio1Vito Leonardo Gallo2Alessandro Pali3Lorenzo Forni4Department of Electrical and Information Engineering, Polytechnic University of Bari, 70125 Bari, ItalyDepartment of Electrical and Information Engineering, Polytechnic University of Bari, 70125 Bari, ItalyDepartment of Electrical and Information Engineering, Polytechnic University of Bari, 70125 Bari, ItalySECO Group SpA, Via A. Grandi 20, 52100 Arezzo, ItalySECO Group SpA, Via A. Grandi 20, 52100 Arezzo, ItalySignal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.https://www.mdpi.com/2079-9292/11/3/475signal integrityhigh-performance PCBPCB interconnection optimizationVIA hole design |
| spellingShingle | Gianfranco Avitabile Antonello Florio Vito Leonardo Gallo Alessandro Pali Lorenzo Forni An Optimization Framework for the Design of High-Speed PCB VIAs Electronics signal integrity high-performance PCB PCB interconnection optimization VIA hole design |
| title | An Optimization Framework for the Design of High-Speed PCB VIAs |
| title_full | An Optimization Framework for the Design of High-Speed PCB VIAs |
| title_fullStr | An Optimization Framework for the Design of High-Speed PCB VIAs |
| title_full_unstemmed | An Optimization Framework for the Design of High-Speed PCB VIAs |
| title_short | An Optimization Framework for the Design of High-Speed PCB VIAs |
| title_sort | optimization framework for the design of high speed pcb vias |
| topic | signal integrity high-performance PCB PCB interconnection optimization VIA hole design |
| url | https://www.mdpi.com/2079-9292/11/3/475 |
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