A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data i...

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Bibliographic Details
Main Authors: Xiqin Tang, Yang Li, Chenxiao Lin, Delong Shang
Format: Article
Language:English
Published: MDPI AG 2022-08-01
Series:Electronics
Subjects:
multiplier architecture
low-power
area-efficient
iterative computing
systolic array
Online Access:https://www.mdpi.com/2079-9292/11/17/2685

Internet

https://www.mdpi.com/2079-9292/11/17/2685

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