A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on...

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Bibliographic Details
Main Authors: Federico Montaño, Tarek Ould-Bachir, Jean Pierre David
Format: Article
Language:English
Published: MDPI AG 2020-11-01
Series:Electronics
Subjects:
real-time simulation
HIL
power electronic circuits
FPGA
latency-insensitive design
data-driven architectures
Online Access:https://www.mdpi.com/2079-9292/9/11/1838

Internet

https://www.mdpi.com/2079-9292/9/11/1838

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