Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

This study presents an accurate model for non-monotonic layout-dependent effects (LDEs) measured using 10nm-class dynamic random access memory technology. To collect the LDE measurement data, a test module with an individually addressable array of 240 transistors has been developed. The proposed tes...

Full description

Bibliographic Details
Main Authors: Seyoung Kim, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, Jaeha Kim
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Addressable array circuit
layout-dependent effects
dynamic random-access memory
scribe lines
shallow trench isolation
Online Access:https://ieeexplore.ieee.org/document/10173498/

Internet

https://ieeexplore.ieee.org/document/10173498/

Similar Items