Device and circuit performance analysis of double gate junctionless transistors at L(g) = 18 nm

Device and circuit performance analysis of double gate junctionless transistors at L(g) = 18 nm

The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V(th) for both n- and p-type of devices. The...

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Bibliographic Details
Main Authors: Chitrakant Sahu, Jawar Singh
Format: Article
Language:English
Published: Wiley 2014-04-01
Series:The Journal of Engineering
Subjects:
CMOS integrated circuits
field effect transistors
SRAM chips
technology CAD (electronics)
semiconductor device models
transient response
invertors
double gate junctionless transistors
DG inversion-mode FETs
drain-induced barrier lowering
steep subthreshold slope
lower OFF state current
pass gate logic
inverter circuit
static random access memory
complementary metal-oxide semiconductor configuration
CMOS configuration
SRAM cell stability
coupled device-circuit methodology
ATLAS TCAD mixed-mode simulator
Online Access:http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0269

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http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0269

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