Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are a...

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Main Authors: KwangHyun Choi, YoungHa Sohn, GeumJu Moon, YongSang Kim, Jae-Hong Jeon, KeeChan Park
Format: Article
Language:English
Published: Taylor & Francis Group 2018-01-01
Series:Journal of Information Display
Subjects:
Online Access:http://dx.doi.org/10.1080/15980316.2017.1417922
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author KwangHyun Choi
YoungHa Sohn
GeumJu Moon
YongSang Kim
Jae-Hong Jeon
KeeChan Park
author_facet KwangHyun Choi
YoungHa Sohn
GeumJu Moon
YongSang Kim
Jae-Hong Jeon
KeeChan Park
author_sort KwangHyun Choi
collection DOAJ
description The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.
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spelling doaj.art-8171be5786304dcbb4f508acb53b3a642022-12-22T03:33:18ZengTaylor & Francis GroupJournal of Information Display1598-03162158-16062018-01-01191455110.1080/15980316.2017.14179221417922Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistorKwangHyun Choi0YoungHa Sohn1GeumJu Moon2YongSang Kim3Jae-Hong Jeon4KeeChan Park5Konkuk UniversityKonkuk UniversityKonkuk UniversitySungkyunkwan UniversityKorea Aerospace UniversityKonkuk UniversityThe low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.http://dx.doi.org/10.1080/15980316.2017.1417922LTPSthin-film transistorpolycrystalline siliconcharge-injectionGIDL
spellingShingle KwangHyun Choi
YoungHa Sohn
GeumJu Moon
YongSang Kim
Jae-Hong Jeon
KeeChan Park
Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
Journal of Information Display
LTPS
thin-film transistor
polycrystalline silicon
charge-injection
GIDL
title Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
title_full Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
title_fullStr Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
title_full_unstemmed Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
title_short Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
title_sort modelling localized charge injection region of the p channel low temperature polycrystalline silicon thin film transistor
topic LTPS
thin-film transistor
polycrystalline silicon
charge-injection
GIDL
url http://dx.doi.org/10.1080/15980316.2017.1417922
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