Efficient BinDCT hardware architecture exploration and implementation on FPGA

Efficient BinDCT hardware architecture exploration and implementation on FPGA

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures...

Full description

Bibliographic Details
Main Authors: Abdessalem Ben Abdelali, Ichraf Chatti, Marwa Hannachi, Abdellatif Mtibaa
Format: Article
Language:English
Published: Elsevier 2016-11-01
Series:Journal of Advanced Research
Subjects:
Binary discrete cosine transform
Discrete cosine transform approximation
Very large scale integration architectures
Hardware implementation
Design exploration
Field programmable gate array
Online Access:http://www.sciencedirect.com/science/article/pii/S2090123216300704

Internet

http://www.sciencedirect.com/science/article/pii/S2090123216300704

Similar Items