High‐Density Vertical Transistors with Pitch Size Down to 20 nm
Abstract Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra‐scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, represe...
| Main Authors: | , , , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-10-01
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| Series: | Advanced Science |
| Subjects: | |
| Online Access: | https://doi.org/10.1002/advs.202302760 |
| _version_ | 1797657818034077696 |
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| author | Zhaojing Xiao Liting Liu Yang Chen Zheyi Lu Xiaokun Yang Zhenqi Gong Wanying Li Lingan Kong Shuimei Ding Zhiwei Li Donglin Lu Likuan Ma Songlong Liu Xiao Liu Yuan Liu |
| author_facet | Zhaojing Xiao Liting Liu Yang Chen Zheyi Lu Xiaokun Yang Zhenqi Gong Wanying Li Lingan Kong Shuimei Ding Zhiwei Li Donglin Lu Likuan Ma Songlong Liu Xiao Liu Yuan Liu |
| author_sort | Zhaojing Xiao |
| collection | DOAJ |
| description | Abstract Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra‐scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high‐density transistors. However, high‐density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade‐offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub‐10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq−1. By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on‐state current of 730 A cm−2. Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high‐density vertical transistors and integrated circuits. |
| first_indexed | 2024-03-11T17:51:06Z |
| format | Article |
| id | doaj.art-840d01a59d0647c7b2b4e008874ea200 |
| institution | Directory Open Access Journal |
| issn | 2198-3844 |
| language | English |
| last_indexed | 2024-03-11T17:51:06Z |
| publishDate | 2023-10-01 |
| publisher | Wiley |
| record_format | Article |
| series | Advanced Science |
| spelling | doaj.art-840d01a59d0647c7b2b4e008874ea2002023-10-18T06:07:54ZengWileyAdvanced Science2198-38442023-10-011029n/an/a10.1002/advs.202302760High‐Density Vertical Transistors with Pitch Size Down to 20 nmZhaojing Xiao0Liting Liu1Yang Chen2Zheyi Lu3Xiaokun Yang4Zhenqi Gong5Wanying Li6Lingan Kong7Shuimei Ding8Zhiwei Li9Donglin Lu10Likuan Ma11Songlong Liu12Xiao Liu13Yuan Liu14Key Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaKey Laboratory for Micro‐Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics Hunan University Changsha 410082 ChinaAbstract Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra‐scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high‐density transistors. However, high‐density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade‐offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub‐10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq−1. By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on‐state current of 730 A cm−2. Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high‐density vertical transistors and integrated circuits.https://doi.org/10.1002/advs.202302760graphene/Au hybrid drainpitch sizevertical field effect transistor |
| spellingShingle | Zhaojing Xiao Liting Liu Yang Chen Zheyi Lu Xiaokun Yang Zhenqi Gong Wanying Li Lingan Kong Shuimei Ding Zhiwei Li Donglin Lu Likuan Ma Songlong Liu Xiao Liu Yuan Liu High‐Density Vertical Transistors with Pitch Size Down to 20 nm Advanced Science graphene/Au hybrid drain pitch size vertical field effect transistor |
| title | High‐Density Vertical Transistors with Pitch Size Down to 20 nm |
| title_full | High‐Density Vertical Transistors with Pitch Size Down to 20 nm |
| title_fullStr | High‐Density Vertical Transistors with Pitch Size Down to 20 nm |
| title_full_unstemmed | High‐Density Vertical Transistors with Pitch Size Down to 20 nm |
| title_short | High‐Density Vertical Transistors with Pitch Size Down to 20 nm |
| title_sort | high density vertical transistors with pitch size down to 20 nm |
| topic | graphene/Au hybrid drain pitch size vertical field effect transistor |
| url | https://doi.org/10.1002/advs.202302760 |
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