A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design
Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Corporation of Research and Industrial Development
2022-12-01
|
| Series: | Iraqi Journal of Industrial Research |
| Subjects: | |
| Online Access: | http://ijoir.gov.iq/ijoir/index.php/jou/article/view/279 |
| _version_ | 1826922766460256256 |
|---|---|
| author | Ahmed Lateef Hameed Maan Hameed Raed Abdulkareem Hasan |
| author_facet | Ahmed Lateef Hameed Maan Hameed Raed Abdulkareem Hasan |
| author_sort | Ahmed Lateef Hameed |
| collection | DOAJ |
| description |
Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power. All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.
|
| first_indexed | 2024-04-13T05:24:04Z |
| format | Article |
| id | doaj.art-8493bfb625864941aaede94738edd836 |
| institution | Directory Open Access Journal |
| issn | 2788-712X |
| language | English |
| last_indexed | 2025-02-17T14:14:30Z |
| publishDate | 2022-12-01 |
| publisher | Corporation of Research and Industrial Development |
| record_format | Article |
| series | Iraqi Journal of Industrial Research |
| spelling | doaj.art-8493bfb625864941aaede94738edd8362024-12-24T05:19:35ZengCorporation of Research and Industrial DevelopmentIraqi Journal of Industrial Research2788-712X2022-12-019310.53523/ijoirVol9I3ID279279A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU DesignAhmed Lateef Hameed0Maan Hameed1Raed Abdulkareem Hasan2Diyala Education Directorate, Ministry of Education – IraqState Commission for Reservoirs and Dams, Ministry of Water Resources – IraqUnit of Renewable Energy Research, Northern Technical University – Iraq Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power. All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version. http://ijoir.gov.iq/ijoir/index.php/jou/article/view/279Tri-state state bufferVLSIGlitchesHazardsSparten |
| spellingShingle | Ahmed Lateef Hameed Maan Hameed Raed Abdulkareem Hasan A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design Iraqi Journal of Industrial Research Tri-state state buffer VLSI Glitches Hazards Sparten |
| title | A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design |
| title_full | A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design |
| title_fullStr | A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design |
| title_full_unstemmed | A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design |
| title_short | A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design |
| title_sort | new technology for reducing dynamic power consumption in 8 bit alu design |
| topic | Tri-state state buffer VLSI Glitches Hazards Sparten |
| url | http://ijoir.gov.iq/ijoir/index.php/jou/article/view/279 |
| work_keys_str_mv | AT ahmedlateefhameed anewtechnologyforreducingdynamicpowerconsumptionin8bitaludesign AT maanhameed anewtechnologyforreducingdynamicpowerconsumptionin8bitaludesign AT raedabdulkareemhasan anewtechnologyforreducingdynamicpowerconsumptionin8bitaludesign AT ahmedlateefhameed newtechnologyforreducingdynamicpowerconsumptionin8bitaludesign AT maanhameed newtechnologyforreducingdynamicpowerconsumptionin8bitaludesign AT raedabdulkareemhasan newtechnologyforreducingdynamicpowerconsumptionin8bitaludesign |