A Minimum Leakage Quasi-Static RAM Bitcell
As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quas...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2011-05-01
|
| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2079-9268/1/1/204/ |
| _version_ | 1811277996014698496 |
|---|---|
| author | Adam Teman Lidor Pergament Omer Cohen Alexander Fish |
| author_facet | Adam Teman Lidor Pergament Omer Cohen Alexander Fish |
| author_sort | Adam Teman |
| collection | DOAJ |
| description | As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV. |
| first_indexed | 2024-04-13T00:26:50Z |
| format | Article |
| id | doaj.art-874d5d8b3aa0468e8eba6ac311accf8c |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-13T00:26:50Z |
| publishDate | 2011-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-874d5d8b3aa0468e8eba6ac311accf8c2022-12-22T03:10:35ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682011-05-011120421810.3390/jlpea1010204A Minimum Leakage Quasi-Static RAM BitcellAdam TemanLidor PergamentOmer CohenAlexander FishAs SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.http://www.mdpi.com/2079-9268/1/1/204/CMOS memory integrated circuitsSRAMleakage suppressionultra low powerdynamic noise margin |
| spellingShingle | Adam Teman Lidor Pergament Omer Cohen Alexander Fish A Minimum Leakage Quasi-Static RAM Bitcell Journal of Low Power Electronics and Applications CMOS memory integrated circuits SRAM leakage suppression ultra low power dynamic noise margin |
| title | A Minimum Leakage Quasi-Static RAM Bitcell |
| title_full | A Minimum Leakage Quasi-Static RAM Bitcell |
| title_fullStr | A Minimum Leakage Quasi-Static RAM Bitcell |
| title_full_unstemmed | A Minimum Leakage Quasi-Static RAM Bitcell |
| title_short | A Minimum Leakage Quasi-Static RAM Bitcell |
| title_sort | minimum leakage quasi static ram bitcell |
| topic | CMOS memory integrated circuits SRAM leakage suppression ultra low power dynamic noise margin |
| url | http://www.mdpi.com/2079-9268/1/1/204/ |
| work_keys_str_mv | AT adamteman aminimumleakagequasistaticrambitcell AT lidorpergament aminimumleakagequasistaticrambitcell AT omercohen aminimumleakagequasistaticrambitcell AT alexanderfish aminimumleakagequasistaticrambitcell AT adamteman minimumleakagequasistaticrambitcell AT lidorpergament minimumleakagequasistaticrambitcell AT omercohen minimumleakagequasistaticrambitcell AT alexanderfish minimumleakagequasistaticrambitcell |