3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact mod...

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Bibliographic Details
Main Authors: Sara Mannaa, Arnaud Poittevin, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Ian O'Connor, Chhandak Mukherjee, Yifan Wang, Houssem Rezgui, Marina Deng, Cristell Maneux, Jonas Muller, Sylvain Pelloquin, Konstantinos Moustakas, Guilhem Larrieu
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Subjects:
3-D electronics
compact model
electrothermal modeling
logic circuit design
vertical nanowire (NW) transistor
Online Access:https://ieeexplore.ieee.org/document/10232986/

Internet

https://ieeexplore.ieee.org/document/10232986/

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