3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs
This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact mod...
| Main Authors: | , , , , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10232986/ |
| _version_ | 1797339226017103872 |
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| author | Sara Mannaa Arnaud Poittevin Cedric Marchand Damien Deleruyelle Bastien Deveautour Alberto Bosio Ian O'Connor Chhandak Mukherjee Yifan Wang Houssem Rezgui Marina Deng Cristell Maneux Jonas Muller Sylvain Pelloquin Konstantinos Moustakas Guilhem Larrieu |
| author_facet | Sara Mannaa Arnaud Poittevin Cedric Marchand Damien Deleruyelle Bastien Deveautour Alberto Bosio Ian O'Connor Chhandak Mukherjee Yifan Wang Houssem Rezgui Marina Deng Cristell Maneux Jonas Muller Sylvain Pelloquin Konstantinos Moustakas Guilhem Larrieu |
| author_sort | Sara Mannaa |
| collection | DOAJ |
| description | This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements. |
| first_indexed | 2024-03-08T09:42:53Z |
| format | Article |
| id | doaj.art-880ac103a0f9440c8b6edc36da7ba0ce |
| institution | Directory Open Access Journal |
| issn | 2329-9231 |
| language | English |
| last_indexed | 2024-03-08T09:42:53Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj.art-880ac103a0f9440c8b6edc36da7ba0ce2024-01-30T00:04:37ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312023-01-019211612310.1109/JXCDC.2023.3309502102329863-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETsSara Mannaa0https://orcid.org/0009-0004-6339-9079Arnaud Poittevin1Cedric Marchand2https://orcid.org/0000-0002-2546-6662Damien Deleruyelle3https://orcid.org/0000-0003-2394-1359Bastien Deveautour4Alberto Bosio5https://orcid.org/0000-0001-6116-7339Ian O'Connor6https://orcid.org/0000-0002-6238-9600Chhandak Mukherjee7https://orcid.org/0000-0002-8206-2779Yifan Wang8Houssem Rezgui9Marina Deng10Cristell Maneux11https://orcid.org/0000-0001-9125-5372Jonas Muller12https://orcid.org/0000-0002-8703-0872Sylvain Pelloquin13Konstantinos Moustakas14Guilhem Larrieu15https://orcid.org/0000-0001-5157-2277École Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceÉcole Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, FranceIMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, FranceIMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, FranceIMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, FranceIMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, FranceIMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, FranceLAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, FranceLAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, FranceLAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, FranceLAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, FranceThis work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.https://ieeexplore.ieee.org/document/10232986/3-D electronicscompact modelelectrothermal modelinglogic circuit designvertical nanowire (NW) transistor |
| spellingShingle | Sara Mannaa Arnaud Poittevin Cedric Marchand Damien Deleruyelle Bastien Deveautour Alberto Bosio Ian O'Connor Chhandak Mukherjee Yifan Wang Houssem Rezgui Marina Deng Cristell Maneux Jonas Muller Sylvain Pelloquin Konstantinos Moustakas Guilhem Larrieu 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3-D electronics compact model electrothermal modeling logic circuit design vertical nanowire (NW) transistor |
| title | 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| title_full | 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| title_fullStr | 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| title_full_unstemmed | 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| title_short | 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| title_sort | 3 d logic circuit design oriented electrothermal modeling of vertical junctionless nanowire fets |
| topic | 3-D electronics compact model electrothermal modeling logic circuit design vertical nanowire (NW) transistor |
| url | https://ieeexplore.ieee.org/document/10232986/ |
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