A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD)...

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Bibliographic Details
Main Authors: Yingdan Jiang, Yang Yu, Lu Tang, Junhao Yang, Yujia Lu, Zongguang Yu
Format: Article
Language:English
Published: MDPI AG 2023-07-01
Series:Electronics
Subjects:
clock generator
multi-modulus divider
automatic frequency calibration
low jitter
Online Access:https://www.mdpi.com/2079-9292/12/14/3196

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https://www.mdpi.com/2079-9292/12/14/3196

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